Architecture of semiconductor memories is roughly divided into two types, namely, open bit line architecture and folded bit line architecture.
In memory devices having memory cell arrays with an open bit line architecture, sense-amplifiers are commonly disposed between sub-arrays of the memory cell arrays. Thereby, each sense-amplifier is commonly connected to two bit lines. The two bit lines, in the following referred to as active bit line and reference bit line, are each connected to memory cells included in two different adjacent sub-arrays of a memory cell array. Further, in the memory cell array having an open bit line architecture, an edge sub-array, i.e., a sub-array that is positioned on the edge, or perimeter, of the memory cell array, has dummy bit lines that are interleaved with normal bit lines. Memory cells connected to the dummy bit lines do not store data during normal operation. Hence, the memory cell efficiency in these edge sub-arrays is reduced from 100% to 50%. These 50% memory cell sub-arrays lead to additional chip area, which makes the memory device more expensive.
Hence, it would be desirable to provide an embodiment to avoid those 50% memory cell sub-arrays with dummy bit lines in order to save chip area for memory device.